In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called "metalization", and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a "dual damascene" technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical "via" at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel oxide layer over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier material is deposited to coat the walls of the first channel openings to prevent diffusion of subsequently deposited conductive material into the oxide layer and the semiconductor. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel oxide layer is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier material is then deposited to coat the via openings and the second channel openings. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride, titanium nitride, and tungsten nitride are used as barrier materials for copper.
The "barrier effectiveness" of a barrier material layer with respect to a conductive material is its ability to prevent diffusion of the conductive material. The barrier effectiveness of a barrier material layer is determined by its thickness, including the thickness uniformity, and its quality, including the number and sizes of defects such as pinholes which form on deposition. To resist copper diffusion, it is found that a minimum barrier material thickness of 5 nm is required. However, to minimize the resistance due to the barrier material layer, it is desirable to maintain a thin barrier material layer. Therefore, it is typical to keep the barrier material layer thickness close to about 5 nm. While it is generally easy to maintain a minimum thickness of 5 nm at the bottom of the channels or vias, it is difficult to do so at the sidewalls of the channels or the vias. Occasionally, there may be insufficient barrier material thickness at the sidewalls which would allow copper to diffuse through, causing damages to adjacent devices. Additionally, defects such as pinholes are often found in a barrier material layer. Copper would diffuse through those defects as well. Furthermore, the stoichimetric composition of an alloyed barrier material, such as tantalum-silicon-nitride (Ta--Si--N), may not be uniform across the feature due to different sputter yields of Ta, Si, and N that may affect the barrier effectiveness as well. Therefore, it is desirable to monitor the barrier effectiveness of a barrier material layer to ensure that thickness is sufficient or that its quality is good enough such that no copper will diffuse through the barrier material layer.
The conventional method to monitor the barrier effectiveness of a barrier material layer for copper is by testing the copper lines and vias for leakage during bias temperature stressing. However, a major drawback of either of these methods is that they are very time-consuming due to the extensive sample preparation procedures required. It is typical to take one to two weeks to obtain the monitor results using either of the above methods. Thus these methods are not practical in a manufacturing environment where fast turn around time of the monitor result is needed to provide feedback so that appropriate corrective actions may be taken prior to the processing of additional wafers.
A solution, which would speed up the evaluation of the barrier effectiveness of barrier material layers with respect to a conductive material, has long been sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and diffusiveness through dielectrics, it is becoming more pressing that a solution be found so that practical monitoring of barrier effectiveness can be performed in a production environment.